Lab Recordings - UE23EC2306
Experiment 1
Design and verify 4-bit binary to gray converter. Implement the same using FPGA/CPLD.
Experiment 10
Write Verilog code for JK flip flop and verify the flip flop.
Experiment 11
Write Verilog code for counter with given input clock and check whether it works as clock divider performing division of clock by 2, 4, 8 and 16. Verify the functionality of the code.
Experiment 12
Implement a basic traffic light controller using Verilog.
Experiment 13
Create a Verilog module to control an 8x8 LED matrix.
Experiment 14
Create a verilog module that simulates rolling a 6-sided digital dice.
Experiment 15
Interface a DAC to FPGA and write Verilog code to generate Sine wave.
Experiment 2
Design and verify 4-bit binary to decimal equivalent. Implement the same using FPGA/CPLD.
Experiment 3
Model in Verilog for a full adder and add functionality to perform logical operations of XOR, XNOR, AND and OR gates. Write test bench with appropriate input patterns to verify the modeled behaviour.
Experiment 4
Implement a basic ALU in Verilog that performs operations such as addition and subtraction.
Experiment 5
Design and verify 8 to 3 priority encoder. Implement the same using FPGA/CPLD. (Behavioural model).
Experiment 6
Design and verify 8 to 1 multiplexer(using case statement and if statements). Implement the same using FPGA/CPLD. (Behavioural model).
Experiment 7
Design and verify 2 to 4 decoder using NAND gates only. Implement the same using FPGA/CPLD. (Structural model).
Experiment 8
Write Verilog code for SR flip flop and verify the flip flop.
Experiment 9
Write Verilog code for D flip flop and verify the flip flop.
